Knowledge-based analogue VLSI layout synthesis

Discusses the incorporation of knowledge-based engineering for automatic layout synthesis in analogue VLSI circuits. Whilst examples are described in terms of CMOS technology, this is not restrictive and the methods described are immediately extensible to other technologies. The study involves a knowledge-based approach combined with traditional algorithmic methods to realise a design system that is capable of automatically producing the layout of an analogue circuit described in netlist form. It is assumed in common with other studies of this problem that the circuit is composed of commonly-encountered functional blocks such as differential pairs, current mirrors, bias stages, output stages, etc. The authors give a detailed discussions of the exact method adopted for the analogue layout synthesis illustrating how knowledge-based engineering is employed to resolve some specific layout problems in analogue circuit synthesis. The system described here treats the layout synthesis problem in a hierarchical manner