DocumentCode
2822853
Title
Architecture for simulation system with consideration of circuit partition
Author
Tanaka, Nobuyuki ; Asai, Hideki
Author_Institution
Dept. of Opt-electron. & Mech. Eng., Shizuoka Univ., Johoku, Hamamatsu, Japan
fYear
1991
fDate
11-14 Jun 1991
Firstpage
2689
Abstract
A description is presented of a circuit simulation system with the dedicated parallel processor SMASH. This system performs model evaluation and LU decomposition, etc., independently at the host computer and SMASH. As a result, it is shown that the simulation time can be reduced to the element model evaluation time. It is also shown that this system is available in case the matrix solution time is dominant over the total simulation time
Keywords
circuit analysis computing; parallel architectures; LU decomposition; SMASH; circuit partition; circuit simulation system; dedicated parallel processor; element model evaluation time; model evaluation; Central Processing Unit; Circuit simulation; Computational modeling; Computer simulation; Equations; Large-scale systems; Matrix decomposition; Nonlinear circuits; Performance evaluation; Sparse matrices;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 1991., IEEE International Sympoisum on
Print_ISBN
0-7803-0050-5
Type
conf
DOI
10.1109/ISCAS.1991.176100
Filename
176100
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