Title :
A 94fps view synthesis engine for HD1080p video
Author :
Chang, Fu-Jen ; Tseng, Yu-Cheng ; Chang, Tian-Sheuan
Author_Institution :
Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan
Abstract :
This paper presents a low-cost and high-throughput view synthesis engine based the view synthesis reference software (VSRS) algorithm. With the horizontal shift mode, we propose the row-based pipelined architecture to save the memory cost for original camera rotation issue. Owing to row- based method, internal Z-buffers for storing depth data can be reduced, and also the external bandwidth can be reduced. With the 90nm technology process, our view synthesis engine can achieve the throughput of 94.5 frame/sec for the HD1080p input with the gate count of 142.9k and the low memory cost of 54.72Kbytes.
Keywords :
cameras; high definition video; signal synthesis; HD1080p video processing; VSRS algorithm; camera rotation; depth data storage; high-throughput view synthesis engine; internal Z-buffers; memory size 54.72 KByte; row-based pipelined architecture; size 90 nm; view synthesis reference software algorithm; Computer architecture; Engines; Hardware; Software; Software algorithms; Streaming media; Throughput; row-based pipelined architecture; virtual view synthesis;
Conference_Titel :
Visual Communications and Image Processing (VCIP), 2011 IEEE
Conference_Location :
Tainan
Print_ISBN :
978-1-4577-1321-7
Electronic_ISBN :
978-1-4577-1320-0
DOI :
10.1109/VCIP.2011.6116009