Parallel hierarchical routing for VLSI on a transputer network

As the problems of design complexity management of VLSI continue to grow, designers have sought methods to reduce the time taken in bringing a system-level design to final silicon. The increasing use of design automation and the exploitation of system hierarchy wherever possible have both been crucial in this context. Due to the computational complexity of the layout process (placement and routing), it takes up a very large part of the time required to design an integrated circuit. Exploiting parallelism is one of the ways of gaining substantial reductions in the time required to perform the layout phase of the VLSI design process, leading to significant reductions in the cost of producing an IC design. The paper describes research into a novel technique for exploiting parallelism in the automatic routing process for hierarchical chip design. A parallel routing model has been set up to be as flexible as possible to that the hardware on which it is based can be used to speed up all phases of the VLSI design cycle