Title :
A 1.7-mW dual-band CMOS frequency synthesizer for low data-rate sub-GHz applications
Author :
Ippolito, Calogero Marco ; Italia, Alessandro ; Palmisano, Giuseppe
Author_Institution :
Fac. di Ing., Univ. di Catania, Catania, Italy
Abstract :
In this paper, an ultra low-power wideband frequency synthesizer is demonstrated in a 90-nm CMOS technology. The circuit is intended for low data-rate sub-GHz transceivers and is based on a programmable integer-TV phase-locked loop. The frequency synthesizer in cooperation with divide-by-two frequency dividers is able to provide quadrature LO signals in the 300-470 MHz and 750-950 MHz RF bands with a 150-kHz frequency step. It provides a phase noise better than -91 dBc/Hz at 150-kHz offset frequency for all the supported channels. The measured settling time is around 350 μS and the reference spurs are lower than -48 dBc. The power consumption of the frequency synthesizer is only 1.7 mW from a 1.2-V supply.
Keywords :
CMOS integrated circuits; frequency dividers; frequency synthesizers; low-power electronics; phase locked loops; phase noise; transceivers; RF bands; divide-by-two frequency dividers; dual-band CMOS frequency synthesizer; offset frequency; phase noise; power 1.7 mW; power consumption; programmable integerTV phase-locked loop; quadrature LO signals; reference spurs; settling time; size 90 nm; sub-GHz transceivers; supported channels; ultra low-power wideband frequency synthesizer CMOS technology; voltage 1.2 V; CMOS integrated circuits; Frequency synthesizers; Inductors; Phase locked loops; Phase noise; Power demand; Voltage-controlled oscillators;
Conference_Titel :
ESSCIRC, 2010 Proceedings of the
Conference_Location :
Seville
Print_ISBN :
978-1-4244-6662-7
DOI :
10.1109/ESSCIRC.2010.5619831
