A critical look at interconnect scaling

The maximum operating frequency of digital VLSI is determined by the speed of the intrinsic logic gates and the response time of the interconnection between the gates. The part played by interconnections has become increasingly important, and is assuming a dominant role at VLSI structures of two micron or less. With shrinking dimensions the system speed of VLSI is more and more determined by the interconnections, which ultimately set a limit to the maximum system operating frequency. That frequency is, even with present structures in the range 2-5 micron, considerably below the maximum count rate of the J-K and/or D bistables. Reduced dimensions serve the main purpose of increasing function density. The faster system performance, additional to that, is often also in demand. The effect of interconnects at the micron-submicron boundary is already such that a reduced geometry is sometimes accompanied by a deterioration in system speed. This paper takes a critical look at interconnect scaling to assess its influence on overall performance. Some alternatives are examined, presenting a choice of interconnect scaling in terms of system speed. The following section looks at the interconnect delay, and is followed by an analysis of scaling. The paper concludes by presenting a choice in scaling to meet specific requirements