A new fast constraint graph generation algorithm for VLSI layout compaction

Author

Fang, Jiaji ; Wong, Joshua S L ; Zhang, Kaihe ; Tang, Pushan

Author_Institution

Dept. of Electron. Eng., Hong Kong Polytech., Kowloon, Hong Kong

fYear

1991

fDate

11-14 Jun 1991

Firstpage

2858

Abstract

A new fast constraint graph generation algorithm called the parallel plane sweep shadowing (PPSS) algorithm is presented for VLSI layout compaction. The algorithm is significant in two aspects. First, instead of analyzing each element shadow individually, PPSS estimates all element shadows simultaneously, which makes it more efficient to generate irredundant constraints. Second, instead of the conventional perpendicular plane sweep method, a parallel plane sweep scheme is developed. This reduces the number of events by half. The experimental results show that PPSS is linear in space and time complexity, and requires about one minute to build a graph from 10000 rectangles on a Sun 3/60 workstation

Keywords

VLSI; circuit layout CAD; graph theory; parallel algorithms; CAD; IC layout design; Sun 3/60 workstation; VLSI layout compaction; constraint graph generation algorithm; element shadow; fast algorithm; irredundant constraints; parallel plane sweep shadowing; Algorithm design and analysis; Compaction; Data structures; Integrated circuit layout; Lamps; Shadow mapping; Solid modeling; Sun; Very large scale integration; Workstations;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1991., IEEE International Sympoisum on

Print_ISBN

0-7803-0050-5

Type

conf

DOI

10.1109/ISCAS.1991.176140

Filename

176140