A new fast constraint graph generation algorithm for VLSI layout compaction

A new fast constraint graph generation algorithm called the parallel plane sweep shadowing (PPSS) algorithm is presented for VLSI layout compaction. The algorithm is significant in two aspects. First, instead of analyzing each element shadow individually, PPSS estimates all element shadows simultaneously, which makes it more efficient to generate irredundant constraints. Second, instead of the conventional perpendicular plane sweep method, a parallel plane sweep scheme is developed. This reduces the number of events by half. The experimental results show that PPSS is linear in space and time complexity, and requires about one minute to build a graph from 10000 rectangles on a Sun 3/60 workstation