Event Recording System in Large Scale Distributed Parallel DSP Processing

Author

Wei Jin ; Liu Feng ; Long Teng

Author_Institution

Dept. of Electron. Eng., Beijing Inst. of Technol., Beijing, China

fYear

2009

fDate

19-20 Dec. 2009

Firstpage

1

Lastpage

4

Abstract

This paper focuses on the monitoring and debugging issues of concurrent DSP processing system in real time large scale distributed parallel scenario. It strives for putting the record and replay technique which stems from the parallel computing realm, into practice for modern high performance embedded computing (HPEC) application and enhancing its feasibility and scalability. Architecture of event recording system based on high performance DSP COTS modules is established, and its core components are designed and implemented, including global clocking domain, event generator and event recorder.

Keywords

digital signal processing chips; electronic engineering computing; embedded systems; parallel processing; program debugging; system monitoring; COTS module; concurrent DSP processing; event generator; event recording system; global clocking; high performance embedded computing; large scale distributed parallel DSP processing; parallel computing; record-and-replay technique; system architecture; system debugging; system monitoring; Clocks; Computer architecture; Debugging; Digital signal processing; Embedded computing; Large-scale systems; Monitoring; Parallel processing; Real time systems; Scalability;

fLanguage

English

Publisher

ieee

Conference_Titel

Information Engineering and Computer Science, 2009. ICIECS 2009. International Conference on

Conference_Location

Wuhan

Print_ISBN

978-1-4244-4994-1

Type

conf

DOI

10.1109/ICIECS.2009.5363735

Filename

5363735