Small-area low-ripple chopper instrumentation amplifier using sample-and-hold circuit

A small-area low-ripple chopper instrumentation amplifier (IA) using a sample-and-hold circuit is proposed. The proposed chopper IA employs a ripple-reduction loop (RRL) to suppress chopper ripple which is generated by the up-modulated offset and 1/f noise. The conventional RRL is not area-efficient since a sensing capacitor occupies a large chip area. Thus, the RRL using the sample-and-hold circuit to reduce the chip area is proposed. The proposed chopper IA is fabricated by using a 0.18 μm CMOS process technology and has a smaller chip area of 0.054 mm² than that of the state-of-the-art design. The measured input-referred ripples with and without the proposed RRL are less than 3.12 mV and 67 μV, respectively.