Two-dimensional digital filtering using a linear processor array

A linear VLSI array is presented for implementing the M-th order 2-dimensional FIR and IIR digital filters. The linear array consists of k M processor elements (PEs). Each PE consists of a control unit, ALU, storage unit, and input/output buffers. The control unit contains microinstructions to be executed by the ALU. Its design is simple and is capable of executing a few instructions such as reading a word from the memory, storing a result in the memory, and performing simple arithmetic operations. The storage element contains O(N) words and can be accessed by the ALU. Input/output buffers are used for receiving data from other PEs and holding results before they are sent to neighboring PEs. The resulting speedup is O(kM), where k is a parameter governed by the tradeoff between the cost of the array and its speedup