A CMOS frequency synthesizer covering the lower and upper bands of 5GHz WLANs

This paper presents the design and experimental results of a 1.8V fractional-N frequency synthesizer. It is implemented in a standard 0.18μm digital CMOS process. A quadrature VCO, providing a 4-phase output, uses combined current and varactor tuning to enable a 1.18GHz tuning range. It covers the entire 5-6GHz frequency span, making it suitable for wireless local area network (WLAN) applications, especially standards defined for both the lower (5.15-5.35GHz) and upper (5.725-5.825GHz) unlicensed bands. The synthesizer phase noise for the lower frequency band is -107dBc/Hz @ 10MHz offset, and for the upper band the phase noise is -91dBc/Hz @ 10MHz. The measured frequency resolution is 5.05MHz, and the settling time is 520ps. All circuitry were optimized for low power consumption. For example, the prescaler/divider combination consumes 4.5mW compared to 19mW reported in [H. R. Rategh, H. Samavati and T. H. Lee (2000)].