• DocumentCode
    2823941
  • Title

    Design of a PLL based frequency synthesizer for multi-standard transceivers

  • Author

    Shawkey, H.A. ; Elsimary, H.A. ; Salama, A.E.

  • Author_Institution
    Electron. Res. Inst., Egypt
  • Volume
    3
  • fYear
    2003
  • fDate
    27-30 Dec. 2003
  • Firstpage
    1150
  • Abstract
    In this paper, the architecture of a dual loop frequency synthesizer for both GSM and DECT standards is described. The implementation for the low frequency loop is presented. The performance of each stage is introduced. The PLL is implemented using CMOS 0.6μm technology with power consumption of 1.7 mW and settling time of 40μsec.
  • Keywords
    CMOS integrated circuits; cellular radio; cordless telephone systems; frequency synthesizers; phase locked loops; transceivers; 0.6 micron; 1.7 mW; 40 mus; CMOS technology; DECT standards; GSM standards; dual loop frequency synthesizer; low frequency loop; multi-standard transceivers; phase locked loop; power consumption; CMOS technology; Energy consumption; Frequency conversion; Frequency locked loops; Frequency synthesizers; GSM; Phase locked loops; Phase noise; Receivers; Transceivers;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Circuits and Systems, 2003 IEEE 46th Midwest Symposium on
  • ISSN
    1548-3746
  • Print_ISBN
    0-7803-8294-3
  • Type

    conf

  • DOI
    10.1109/MWSCAS.2003.1562497
  • Filename
    1562497
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2823941