DocumentCode
2824206
Title
GaAs trickle transistor dynamic logic
Author
Hoe, David H K ; Salama, C. Andre T
Author_Institution
Dept. of Electr. Eng., Toronto Univ., Ont., Canada
fYear
1991
fDate
11-14 Jun 1991
Firstpage
3007
Abstract
A GaAs dynamic logic gate is proposed which uses a trickle transistor to compensate for leakage from the precharged node. This trickle transistor dynamic logic (TTDL) circuit can be configured as a domino logic gate and a differential cascode voltage switch logic gate. Delay chains were implemented in a 1 μm GaAs E/D process to characterize the gates. In addition, the TTDL gates were used to implement a four-bit carry-lookahead adder. The adder has a circuit delay of 0.8 ns and a power dissipation of 130 mW
Keywords
III-V semiconductors; Schottky gate field effect transistors; adders; field effect integrated circuits; gallium arsenide; integrated logic circuits; large scale integration; 0.8 ns; 1 micron; 130 mW; 4 bit; E/D process; GaAs; TTDL; adder circuits; circuit delay; delay chains; differential cascode voltage switch logic gate; domino logic gate; dynamic logic gate; four-bit carry-lookahead adder; gate delay; power dissipation; semiconductors; trickle transistor dynamic logic; Dynamic range; FETs; Gallium arsenide; Gate leakage; Logic circuits; Logic devices; Logic gates; MESFETs; Switches; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 1991., IEEE International Sympoisum on
Print_ISBN
0-7803-0050-5
Type
conf
DOI
10.1109/ISCAS.1991.176177
Filename
176177
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