All digital modulation bandwidth extension technique for narrow bandwidth analog fractional-N PLL

An all digital modulation bandwidth extension technique for a conventional charge pump PLL is proposed. By modulating data through fractional divider in feedback path and digital-to-frequency path in VCO all digitally, PLL´s loop bandwidth can therefore be optimized for noise filtering while high data rate modulation is still obtained. The gain mismatch between input and digital-to-frequency path in VCO is calibrated based on the proposed conservation principle for a mixed mode system. The chip demonstrates the modulation bandwidth for a narrow bandwidth fractional-N PLL is extended by 70 times. The chip is implemented in 65nm CMOS process with 1.2V supply. The overhead of bandwidth extension circuitry is only 0.05mm².