Design of a fully integrated concurrent triple-band CMOS low noise amplifier

Author

Jou, Christina F. ; Cheng, Kuo-Hua ; Lu, Eing-Tsang ; Wang, Yang

Author_Institution

Dept. of Commun. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan

Volume

3

fYear

2003

fDate

27-30 Dec. 2003

Firstpage

1239

Abstract

A fully integrated concurrent triple-band low noise amplifier (LNA) is designed and presented in this paper. It has been fabricated using TSMC 0.25-μm mixed-signal CMOS process. A two stage topology with bias-current reuse technique has been used to simultaneously achieve high gain and good matching without large amount of power consumption at all three desired band -1.8GHz, 2.45GHz and 5.25GHz. It also achieves similar good performance at these three different frequencies. We will show its post simulation results to demonstrate this good performance. The LNA exhibits input matching to 50ohm with S₁₁ of -10.6dB at 1.8GHz, -10.4dB at 2.45GHz and -19.9dB at 5.25GHz as well as output matching to 50ohm with S₂₂of -15.5dB, -12.5dB and -12.0dB, respectively. And it provides forward gain (S₂₁) of 10.1dB, 10.8dB and 11.8dB with noise figure of 3.72dB, 4.76dB and 6.38dB respectively while drawing 39mW from a 2.5V supply voltage.

Keywords

CMOS integrated circuits; UHF amplifiers; integrated circuit design; microwave amplifiers; 0.25 micron; 1.8 GHz; 10.1 dB; 10.8 dB; 11.8 dB; 2.45 GHz; 2.5 V; 3.72 dB; 39 mW; 4.76 dB; 5.25 GHz; 6.38 dB; CMOS low noise amplifier; TSMC mixed-signal CMOS; bias current reuse technique; triple band low noise amplifier; CMOS process; Costs; Dual band; Impedance; Low-noise amplifiers; Noise figure; Radio frequency; Transceivers; Wideband; Wireless communication;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2003 IEEE 46th Midwest Symposium on

ISSN

1548-3746

Print_ISBN

0-7803-8294-3

Type

conf

DOI

10.1109/MWSCAS.2003.1562519

Filename

1562519