Title :
A 9 pW/Hz adjustable clock generator with 3-decade tuning range for dynamic power management in subthreshold SCL systems
Author :
Tajalli, Armin ; Leblebici, Yusuf
Author_Institution :
Microelectron. Syst. Lab. (LSM), Ecole Polytech. Fed. de Lausanne (EPFL), Lausanne, Switzerland
Abstract :
A widely-tunable and power-scalable clock generator for ultra-low power (ULP) applications is presented. Benefitting from a novel self-adjustable loop frequency response, the proposed phase-locked loop based clock generator exhibits a tuning range of three decades. Implemented in 0.13 μm CMOS, the circuit occupies 0.06 mm2, while its power dissipation is 9 pW/Hz, proportional to the output clock frequency with 350 nW stand-by power. The circuit remains stable with scalable dynamics for frequency steps (upward and downward) as large as a factor of ×1024. The presented clock generator has been designed to be compatible with subthreshold source-coupled logic (STSCL) topology that can be used for ultra-low power applications such as in bio-medical systems.
Keywords :
CMOS logic circuits; clocks; low-power electronics; network topology; phase locked loops; 3-decade tuning range; CMOS; adjustable clock generator; dynamic power management; phase-locked loop; power-scalable clock generator; self-adjustable loop frequency response; size 0.13 mum; subthreshold SCL systems; subthreshold source-coupled logic topology; ultra-low power applications; widely-tunable clock generator; Charge pumps; Clocks; Generators; Phase locked loops; Power dissipation; Topology; Tuning;
Conference_Titel :
ESSCIRC, 2010 Proceedings of the
Conference_Location :
Seville
Print_ISBN :
978-1-4244-6662-7
DOI :
10.1109/ESSCIRC.2010.5619884
