Design methodology for direct mapping of iterative algorithms on array architectures

A systematic methodology for mapping a class of iterative algorithms onto processor array architectures is presented. The concept of the array architecture is combined efficiently with the existing knowledge of compiler techniques. It is considered as an initial description of the iterative algorithm Fortran-like nested loops, without the requirement of transforming it into any intermediate form such as uniform recurrent equations. The principles of Lamport´s coordinate method are used. Depending on the systolic or non-systolic structure of the algorithm and/or the multidimensional mapping, the resulting architectures can be either regular arrays or piecewise regular arrays. The important subclass of algorithm known as weak single assignment codes is treated in an optimal way