• DocumentCode
    2824550
  • Title

    3GHz, 74mW 2-level Karatsuba 64b Galois field multiplier for public-key encryption acceleration in 45nm CMOS

  • Author

    Mathew, Sanu ; Kounavis, Michael ; Sheikh, Farhana ; Hsu, Steven ; Agarwal, Amit ; Kaul, Himanshu ; Anders, Mark ; Berry, Frank ; Krishnamurthy, Ram

  • Author_Institution
    Intel Labs., Intel Corp., Hillsboro, OR, USA
  • fYear
    2010
  • fDate
    14-16 Sept. 2010
  • Firstpage
    198
  • Lastpage
    201
  • Abstract
    A Karatsuba-based 64b Galois field multiplier for on-die acceleration of public-key encryption is fabricated in 1.1V, 45nm CMOS and occupies 0.021mm2. 2-level Karatsuba design using interleaved 32b multipliers and folded datapath organization results in single-cycle latency at 3GHz operation with total power consumption of 74mW and 32% area reduction over conventional multipliers, resulting in 3.2x speedup of Diffie-Helman key exchange workloads.
  • Keywords
    CMOS integrated circuits; Galois fields; public key cryptography; 2-level Karatsuba 64b Galois field multiplier; 2-level Karatsuba design; CMOS; Diffie-Helman key exchange workloads; folded datapath; frequency 3 GHz; interleaved 32b multipliers; on-die acceleration; power 74 mW; public-key encryption acceleration; size 45 nm; Acceleration; CMOS integrated circuits; Clocks; Encryption; Galois fields; Public key; Software;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    ESSCIRC, 2010 Proceedings of the
  • Conference_Location
    Seville
  • ISSN
    1930-8833
  • Print_ISBN
    978-1-4244-6662-7
  • Type

    conf

  • DOI
    10.1109/ESSCIRC.2010.5619895
  • Filename
    5619895
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2824550