Built-in self parallel testing for functional faults in megabit RAMs

Author

Hur, Y.D. ; Cho, Hyo Moon ; Lee, Joong Ho ; Cho, Sang Bock

Author_Institution

Dept. of Electron. Eng., Ulsan Univ., South Korea

fYear

1991

fDate

11-14 Jun 1991

Firstpage

3090

Abstract

A test algorithm and design scheme are proposed for a built-in self testing technique for functional faults in semiconductor random access memories. The test algorithm detects stuck-at and pattern sensitive faults over a neighborhood of nine cells. An n-bit memory is composed of p square sub-arrays, and this algorithm takes 2310 (n/p)^1/2 testing cycles. The row address generator, test pattern generator, parallel pattern loader, and parallel data comparator are added to the conventional RAM circuits for the built-in self testing function

Keywords

built-in self test; fault location; integrated circuit testing; integrated memory circuits; random-access storage; built-in self testing technique; functional faults; megabit RAMs; n-bit memory; parallel data comparator; parallel pattern loader; pattern sensitive faults; row address generator; semiconductor random access memories; square sub-arrays; stuck-at faults; test algorithm; test pattern generator; testing cycles; Automatic testing; Circuit faults; Circuit testing; Electronic equipment testing; Fault detection; Logic testing; Moon; Random access memory; Read-write memory; Semiconductor device testing;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1991., IEEE International Sympoisum on

Print_ISBN

0-7803-0050-5

Type

conf

DOI

10.1109/ISCAS.1991.176201

Filename

176201