A 0.9mW PLL integrated in an ultra-low-power SoC for WPAN and WBAN applications

Author

Devita, G. ; Wong, A.C.W. ; Kasparidis, N. ; Corbishley, P. ; Burdett, A. ; Paddan, P.

Author_Institution

Toumaz Technol. Ltd., Abingdon, UK

fYear

2010

fDate

14-16 Sept. 2010

Firstpage

158

Lastpage

161

Abstract

In this paper we present a low-power frequency synthesizer fabricated as a part of the ultra low-power wireless transceiver system named TELRAN™. The synthesizer consists of an integer-N Phase Locked Loop (PLL), operating in the frequency range 766-850MHz, with automatic tank selection hardware state machine. The System on Chip (SoC) has been fabricated in a 0.13μm CMOS technology. The PLL occupies an area of 0.98mm², dissipating 0.87mA from a 1V supply. The measured phase noise at 10kHz and 100kHz from the carrier is better than -60dBc and -93dBc, respectively.

Keywords

body area networks; frequency synthesizers; personal area networks; system-on-chip; CMOS technology; PLL; TELRAN; WBAN application; WPAN application; automatic tank selection hardware state machine; low power frequency synthesizer; phase locked loop; system on chip; ultra low power SoC; ultra low power wireless transceiver system; wireless body area network; wireless personal area network; Frequency shift keying; Phase locked loops; Phase noise; System-on-a-chip; Tuning; Voltage-controlled oscillators;

fLanguage

English

Publisher

ieee

Conference_Titel

ESSCIRC, 2010 Proceedings of the

Conference_Location

Seville

ISSN

1930-8833

Print_ISBN

978-1-4244-6662-7

Type

conf

DOI

10.1109/ESSCIRC.2010.5619905

Filename

5619905