Transaction level model-based design methodology for fast architectural exploration and verification

System-on-chip designs are highly complex due to increase gate counts and hardware/software interactions. Development of performance, cost and power sensitive devices push for a design environment that can evaluate the system as a whole against these objectives. Transaction-level modeling (TLM) provides a well-defined structure for evaluating these architectural tradeoffs. In this paper, we described our SystemC TLM based approach using a mixture of Mathworks, CoWare and Synopsys tools, from algorithm analysis, co-design to co-verification, in the design of a low-power CORDIC engine. Using this design methodology and MIBench FFT/IFFT as our metric, we were able to achieve close to ideal performance speedup and a 95% power reduction.