Title :
A new low latency Viterbi decoder core
Author :
Shebaita, Ahmed ; Khairy, Mohamed ; Salama, Ali Ezzat ; Ashour, Mhamoud
Author_Institution :
Design Center, Egyptian Atomic Energy Authorization, Cairo, Egypt
Abstract :
In this paper, a novel Viterbi decoder core is presented. The new low-complexity core is optimized to minimize the decoding latency, thus relaxing the delay/performance/area tradeoff. An FPGA implementation of a fully parallel Viterbi decoder based on the new core is presented.
Keywords :
Viterbi decoding; field programmable gate arrays; FPGA; Viterbi decoder core; decoding latency; Authorization; Bit error rate; Block codes; Convolutional codes; Decoding; Delay; Design engineering; Field programmable gate arrays; Power engineering and energy; Viterbi algorithm;
Conference_Titel :
Circuits and Systems, 2003 IEEE 46th Midwest Symposium on
Print_ISBN :
0-7803-8294-3
DOI :
10.1109/MWSCAS.2003.1562551
