DocumentCode :
2825
Title :
Algorithm and Architecture Design of Bandwidth-Oriented Motion Estimation for Real-Time Mobile Video Applications
Author :
Hsieh, Jui-Hung ; Chang, Tian-Sheuan
Author_Institution :
Dept. of Electron. Eng., Nat. Chiao-Tung Univ., Hsinchu, Taiwan
Volume :
21
Issue :
1
fYear :
2013
fDate :
Jan. 2013
Firstpage :
33
Lastpage :
42
Abstract :
This paper proposes a data bandwidth-oriented motion estimation design for resource-limited mobile video applications using an integrated bandwidth rate distortion optimization framework. This framework predicts and allocates the appropriate data bandwidth for motion estimation under a limited bandwidth supply to fit a dynamically changing bandwidth supply. The simulation results show that our proposed algorithm can achieve 66% and 41% memory bandwidth savings while maintaining an equivalent rate-distortion performance and meeting real-time targets, when compared with conventional approaches for low-motion and high-motion D1 (704 ×  576)-size video, respectively. The final implementation costs 122 K gate counts with TSMC 0.13-μ m CMOS technology and consumes 74 mW of power for D1 resolution at 30 frames/s which is 40% of that achieved in previous designs.
Keywords :
CMOS integrated circuits; mobile computing; motion estimation; video coding; video signal processing; CMOS technology; algorithm design; architecture design; data bandwidth-oriented motion estimation design; integrated bandwidth rate distortion optimization framework; memory bandwidth savings; real-time mobile video applications; resource-limited mobile video applications; Algorithm design and analysis; Bandwidth; Computer architecture; Encoding; Hardware; Strontium; Vectors; H.264/AVC; VLSI architecture; low power; memory bandwidth; motion estimation; video coding;
fLanguage :
English
Journal_Title :
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
Publisher :
ieee
ISSN :
1063-8210
Type :
jour
DOI :
10.1109/TVLSI.2011.2178439
Filename :
6135844
Link To Document :
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