FPGA implementation of modified radix 2 SRT division algorithm

Author

Ibrahem, Attif A. ; Elsimary, Hamed ; Salama, Aly E.

Author_Institution

Electron. Res. Inst., Cairo, Egypt

Volume

3

fYear

2003

fDate

27-30 Dec. 2003

Firstpage

1419

Abstract

The flexibility of field programmable gate arrays (FPGAs) can provide arithmetic intensive applications with the benefits of custom hardware but without the high cost of custom silicon implementations. In this paper, we present the adaptation of modified radix 2 division algorithm by Cquillan, et al. (1993) for lookup table based FPGAs implementation. For this modified scheme, the result digits and the residuals are computed concurrently and the computations in adjacent rows are overlapped. The implementation has been done with Xilinx technology and FPGA-Advantage CAD tools.

Keywords

VLSI; circuit CAD; digital arithmetic; field programmable gate arrays; integrated circuit design; FPGA; FPGA-Advantage CAD tool; Xilinx technology; arithmetic intensive applications; custom hardware; custom silicon implementation; field programmable gate arrays; modified radix 2 SRT division algorithm; two-digit quotient selection; Algorithm design and analysis; Arithmetic; Concurrent computing; Costs; Field programmable gate arrays; Hardware; Silicon; Table lookup; Testing; Very large scale integration; Field programmable gate arrays (FPGAs); SRT division; division; two-digit quotient selection;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2003 IEEE 46th Midwest Symposium on

ISSN

1548-3746

Print_ISBN

0-7803-8294-3

Type

conf

DOI

10.1109/MWSCAS.2003.1562561

Filename

1562561