Title :
Automatic synthesis of parallel processors
Author :
Kidwell, Michelle D. ; Raj, Vijay K.
Author_Institution :
Texas Univ., Arlington, TX, USA
Abstract :
The system described accepts as input a high level language behavioral description of a multiprocessor computer system and outputs a specification for an array of parallel processors. The processors are then designed by the use of a high level architecture synthesis system. The behavioral description may contain loops nested to any depth. User specified constraints, limitations, and interconnection configurations may also be input
Keywords :
formal specification; parallel architectures; parallel processing; behavioral description; high level architecture synthesis system; high level language; interconnection configurations; multiprocessor computer system; nested loops; parallel processors; specification; user specified constraints; Costs; Systolic arrays; Time measurement; Velocity measurement;
Conference_Titel :
Circuits and Systems, 1991., IEEE International Sympoisum on
Print_ISBN :
0-7803-0050-5
DOI :
10.1109/ISCAS.1991.176222
