A primary planner for high-level architectural synthesis

The authors present an integrated internal representation, a primary plan, as a basis for the automatic synthesis of a register transfer architecture from a behavioural description. The structure of a prototype synthesis system is presented, and the generation of the primary plan is discussed in detail. The system operates by adopting a hierarchical approach and transforming the initial abstract representation of the plan to a hardware structure which meets specified speed and hardware constraints. An example is given showing how different user constraints produce alternative architectures