Title :
A high-speed/low-power architecture for 1D discrete biorthogonal wavelet transform
Author :
Uzun, I.S. ; Amira, A. ; Bouridane, Ahmed
Author_Institution :
Sch. of Comput. Sci., Queen´´s Univ., Belfast, UK
Abstract :
Biorthogonal wavelets offer improved coding gain and an efficient treatment of boundaries in signal coding applications. In this paper, we propose a scalable pipelined architecture that performs 1D discrete biorthogonal wavelet transform (DBWT) with K decomposition levels in N0/2 clock cycles. Therefore, it is at least twice as fast as other known DBWT architectures. The performance of the architecture has been verified and evaluated by implementations on Xilinx Virtex-2000E FPGA chip. Very high data-throughput rates up to 320 MegaSamples/sec, with efficient hardware utilisation have been achieved.
Keywords :
VLSI; clocks; digital signal processing chips; field programmable gate arrays; hardware-software codesign; wavelet transforms; 1D discrete biorthogonal wavelet transform; K decomposition; VLSI; Xilinx Virtex-2000E FPGA chip; clock cycles; coding gain; hardware design; high data-throughput rates; high-speed low-power architecture; scalable pipelined architecture; signal coding; signal processing; Carbon capture and storage; Clocks; Computer architecture; Discrete wavelet transforms; Equations; Field programmable gate arrays; Filter bank; Hardware; Low pass filters; Very large scale integration;
Conference_Titel :
Circuits and Systems, 2003 IEEE 46th Midwest Symposium on
Print_ISBN :
0-7803-8294-3
DOI :
10.1109/MWSCAS.2003.1562569