DocumentCode
2825403
Title
A simulation-based temporal assertion checker for PSL
Author
Chang, Kai-Hui ; Tu, Wei-Ting ; Yeh, Yi-Jong ; Kuo, Sy-Yen
Author_Institution
Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan
Volume
3
fYear
2003
fDate
27-30 Dec. 2003
Firstpage
1528
Abstract
A simulation-based temporal assertion verification engine for PSL (property specification language), called Tempral Wizard, is proposed in this paper. It is very efficient because its time and space complexity are both O(n). A new concept, tag, is introduced in Tempral Wizard and it handles the forall operator elegantly.
Keywords
computational complexity; electronic design automation; formal verification; simulation; temporal logic; PSL; Tempral Wizard; property specification language; space complexity; temporal assertion verification engine; time complexity; Circuit simulation; Circuit synthesis; Clocks; Engines; Formal specifications; Hardware design languages; Logic; Specification languages; Terminology; Yarn;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 2003 IEEE 46th Midwest Symposium on
ISSN
1548-3746
Print_ISBN
0-7803-8294-3
Type
conf
DOI
10.1109/MWSCAS.2003.1562587
Filename
1562587
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