Implementing low-power dynamic adders in MTCMOS technology

New low power dynamic MTCMOS full-adder cells have been proposed in this paper. Eight bit Domino and TSPC (True Single phase clock) adder circuits have been designed in 45 nm Multi-threshold CMOS Technology. The proposed MTCMOS dynamic adder circuits are faster as compared to static CMOS logic circuits. Due to the high-V_T sleep transistor added, the leakage power of the circuits is also minimized by 94% to 96%. Simulation results verify that the circuits operate with high speed due to the low-V_T transistors used in the evaluation block and also achieve a significant reduction in leakage power. The ground bouncing noise of the eight bit MTCMOS TSPC adder is also evaluated. It is shown that the ground bouncing noise of the circuit reduces with increase in sleep signal rise delay.