The performance of a DRAM system with merged pages

This paper evaluates the performance effect of DRAM page size in workstation configurations. DDR-SDRAM and direct rambus architectures are simulated. For the simulated bus configurations and applications, the highest performance is obtained by minimizing the page size and maximizing the number of banks. Large variation in DRAM system performance is observed for different applications. Furthermore, the selection of the width of the devices can strongly affect the DRAM performance. In addition to the DRAM system simulations, the spatial locality of the DRAM access stream is analyzed. The analysis results show that there is little spatial locality beyond the DRAM native page sizes used in the simulations. This supports the DRAM simulation results. Due to varying nature of DRAM performance, simulation of DRAM system or analysis of the application is essential before the implementation.