Title :
Effect of scaling on stand-by current in PD-SOI pseudo-nMOS circuits
Author :
Sivagnaname, Jayakumaran ; Brown, Richard B.
Author_Institution :
Dept. of Electr. Eng. & Comput. Sci., Michigan Univ., Ann Arbor, MI, USA
Abstract :
As technology is scaled, the leakage currents pose significant problems during active and stand-by modes of operation. This scenario leads us to re-evaluate less commonly used logic styles for future use. In this paper we consider the pseudo-nMOS logic circuits and evaluate the effect of scaling on the stand-by current in 130nm and 90nm PD-SOI technology.
Keywords :
MOS logic circuits; leakage currents; scaling circuits; silicon-on-insulator; 130 nm; 90 nm; PD-SOI pseudo-nMOS circuits; PD-SOI technology; active mode; leakage current; pseudo-nMOS logic circuits; scaling effect; stand-by current; stand-by mode; Adders; CMOS logic circuits; CMOS technology; Flip-flops; Latches; Leakage current; Logic circuits; MOSFETs; Size control; Transistors;
Conference_Titel :
Circuits and Systems, 2003 IEEE 46th Midwest Symposium on
Print_ISBN :
0-7803-8294-3
DOI :
10.1109/MWSCAS.2003.1562595
