A processor approach for video signal processing

The authors present a signal processor, that is designed as a basic cell for multiprocessor arrays. A high-instruction-rate, 12-b data width, and a RISC (reduced instruction set computer) cell architecture make the processor suitable for the requirements of video signal processing. The multiprocessor array belongs to the class of the multiple-instruction multiple-data (MIMD) principle, which offers high performance and flexibility due to the programmability of each cell. The obtained MIMD topology is an orthogonal net of processors where each processor communicates with its neighbors