A multiprocessor system for interframe hierarchical address-vector quantization

Author

Choo, Chang Y. ; Nasrabadi, Nasser M. ; Desjarlais, Frank J.

Author_Institution

Dept. of Electr. Eng., Worcester Polytech. Inst., MA, USA

fYear

1991

fDate

11-14 Jun 1991

Firstpage

61

Abstract

The authors report on an ongoing design and performance evaluation of an interframe hierarchical address-vector quantization (IHAVQ) system for coding a sequence of moving images. The image coding system exploits the inherent parallelism of the IHAVQ algorithm by using a tree-structured multiprocessor architecture for distributed motion-compensated image data. An implementation of the system using three TM5320C25 DSP microprocessors is described, and its performance is analyzed

Keywords

computerised picture processing; data compression; digital signal processing chips; encoding; parallel algorithms; parallel processing; IHAVQ algorithm; TM5320C25 DSP microprocessors; distributed motion-compensated image; image coding; interframe hierarchical address-vector quantization; moving image sequence coding; multiprocessor system; parallelism; tree-structured multiprocessor architecture; Computer architecture; Concurrent computing; Digital signal processing; Image coding; Image segmentation; Microprocessors; Motion compensation; Multiprocessing systems; Performance analysis; Vector quantization;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1991., IEEE International Sympoisum on

Print_ISBN

0-7803-0050-5

Type

conf

DOI

10.1109/ISCAS.1991.176273

Filename

176273