Timing optimization of multi-phase sequential logic

An algorithm which improves the timing optimization of multiphase sequential logic is presented as a set of extensions to the combinational logic optimization tool, misII. The algorithms yield improvements that are 20% better than what is achievable using only combinational logic optimization tools that do not move logic across latches. Furthermore, 65% of the improvements possible are achieved in the most idealized case. Results on simple two-phase circuits show average input to output delay improvements of almost 20% with area penalties of less than 12%. For a four-phase controller used in a processor it yields an improvement in cycle time of 21% with an area penalty of 21%