Title :
Logic transformations for synchronous logic synthesis
Author :
De Micheli, G. ; Yip, Roger
Author_Institution :
Comput. Syst. Lab., Stanford Univ., CA, USA
Abstract :
An approach to logic synthesis of digital synchronous sequential circuits is presented. Algorithms are described for minimizing the area of synchronous combinational and/or sequential circuits under cycle time constraints and for minimizing the cycle time under area constraints. It is shown how to optimize concurrently the circuit equations and the register position by a set of algorithms based on logic transformations. An implementation of the algorithms in the program Minerva is described, and experimental results are reported
Keywords :
combinatorial circuits; logic CAD; sequential circuits; combinational circuits; digital synchronous sequential circuits; logic transformations; program Minerva; synchronous logic synthesis; Circuit synthesis; Clocks; Combinational circuits; Integrated circuit interconnections; Integrated circuit synthesis; Logic circuits; Logic design; Network synthesis; Registers; Sequential circuits;
Conference_Titel :
System Sciences, 1990., Proceedings of the Twenty-Third Annual Hawaii International Conference on
Conference_Location :
Kailua-Kona, HI
DOI :
10.1109/HICSS.1990.205141
