Irredundant sequential machines via optimal logic synthesis

It is shown that optimal sequential logic synthesis can produce irredundant, fully testable finite-state machines. Synthesizing a sequential circuit from a state-transition-graph description involves the steps of state minimization, state assignment, and logic optimization. It is also shown that 100% testability can be ensured without the addition of extra logic and without constraints on the state assignment and logic optimization. There is no area/performance penalty associated with this approach. This technique can be used in conjunction with previous approaches to ensure that the synthesized machine is easily testable. Given a state-transition-graph specification, a logic-level automation that is fully testable for all single stuck-at faults in the combinational logic without access to the memory elements can be synthesized. These procedures represent an alternative to a scan-design methodology, without the latter´s usual area and performance penalty