A unified approach to the synthesis of fully testable sequential machines

The authors unify and extend the various approaches to synthesizing fully testable sequential circuits that can be modeled as finite state machines (FSMs). Classes of redundancies are identified, and equivalent-state redundancies are isolated as those most difficult to eliminate. It is then shown that the essential problem behind equivalent-state redundancies is the creation of valid/invalid state pairs. Techniques are presented for developing differentiating sequences for valid/invalid state pairs created by a fault, as well as techniques for retaining these sequences in the presence of that fault. The notion of fault-effect disjointness is used to investigate optimal and constrained synthesis procedures. Techniques used in this investigation include fault simulation, Boolean covering, algebraic factorization, and state assignment. Experimental results using the synthesis procedures as well as comparisons to previous approaches are presented