• DocumentCode
    2825858
  • Title

    Heterogeneous reconfigurable systems

  • Author

    Rabaey, Jan M. ; Abnous, Arthur ; Ichikawa, Yuji ; Seno, Kazunori ; Wan, Marlene

  • Author_Institution
    Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
  • fYear
    1997
  • fDate
    3-5 Nov 1997
  • Firstpage
    24
  • Lastpage
    34
  • Abstract
    The continually increasing integration density of integrated circuits portrays important paradigm shifts in next-generation designs, especially in the direction of systems-on-a-chip. Hybrid architectures mixing a variety of computational models are bound to be integrated on a single die. This opens the door for creative high-performance low-energy solutions to the programming problem using techniques such as reconfiguration to construct optimized architectures for a given computational problem. Exploiting the opportunities offered by these architectural innovations obviously requires a clear understanding of the trade-off´s offered by the various architectural models and styles, as well as a well-thought out design methodology, combining high-level prediction and analysis tools with partitioning, optimization and mapping techniques. This paper presents an overview of opportunities of these reconfigurable architectures in the architecture domain
  • Keywords
    microprocessor chips; optimisation; reconfigurable architectures; computational models; computational problem; heterogeneous reconfigurable systems; high-level prediction; hybrid architectures; integrated circuits; integration density; low-energy solutions; mapping techniques; next-generation designs; optimization; optimized architectures; overview; partitioning; reconfigurable architectures; reconfiguration; systems-on-a-chip; Circuits; Computational modeling; Computer architecture; Design methodology; Design optimization; High performance computing; Microprocessors; Multimedia systems; Predictive models; Technological innovation;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Signal Processing Systems, 1997. SIPS 97 - Design and Implementation., 1997 IEEE Workshop on
  • Conference_Location
    Leicester
  • ISSN
    1520-6130
  • Print_ISBN
    0-7803-3806-5
  • Type

    conf

  • DOI
    10.1109/SIPS.1997.625684
  • Filename
    625684