DocumentCode :
2825885
Title :
Delay testing based on transition faults propagated to all reachable outputs
Author :
Vaidya, Bhushan ; Tahoori, Mehdi B.
Author_Institution :
Northeastern Univ., Boston, MA, USA
fYear :
2004
fDate :
38102
Firstpage :
67
Lastpage :
75
Abstract :
Data from the test floor has shown that transition faults propagated to all reachable outputs (TARO) is more effective in detecting defective chips compared to conventional transition faults [Tseng et al. 2001]. This paper describes an efficient approach to generate tests pattern based on TARO metric using Boolean satisfiability. The problem of test pattern generation is converted to an instance of Boolean satisfiability and the recent development in the design of efficient SAT solvers has helped to speed up the process of test generation extensively. Experimental results on several benchmarks show the effectiveness of this technique.
Keywords :
automatic test pattern generation; combinational circuits; delays; fault simulation; integrated circuit testing; logic testing; ATPG; Boolean satisfiability; SAT solvers; TARO metric; automatic test pattern generation; benchmarks; defective chips detection; delay testing; test floor; transition faults propagated to all reachable outputs; Automatic test pattern generation; Benchmark testing; Circuit faults; Circuit testing; Clocks; Fault detection; Frequency; Propagation delay; Test pattern generators; Timing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Current and Defect Based Testing, 2004. DBT 2004. Proceedings. 2004 IEEE International Workshop on
Print_ISBN :
0-7803-8950-6
Type :
conf
DOI :
10.1109/DBT.2004.1408958
Filename :
1408958
Link To Document :
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