Title :
A high speed 2-D DCT/IDCT processor
Author :
Li, Weiping ; Slawecki, Darren
Author_Institution :
CSEE Dept., Lehigh Univ., Bethlehem, PA, USA
Abstract :
Recently, a novel algorithm to compute the discrete cosine transform (DCT) and its inverse (IDCT) was derived by W. Li (1991). Based on this algorithm, a high-speed 8×8 2-D DCT/IDCT processor chip was designed. In the present work, the algorithm is briefly outlined; the chip architecture is presented; and some circuit design issues are discussed. The chip measures 7.9×9.2 mm2. It is designed using the MOSIS 2-μm SCMOS technology. It takes 16-b inputs, uses 16-b internal memory for coefficients and data, and generates 16-b outputs. A single input line determines if the chip computes the DCT or the IDCT. The chip is highly pipelined with a latency of 135 cycles and a throughput of 55 MHz, which is equivalent to computing 880 million multiplies and 770 million adds per second
Keywords :
CMOS integrated circuits; computerised signal processing; digital signal processing chips; pipeline processing; transforms; 16 bit; 2 micron; 2D processor chip; 55 MHz; DCT/IDCT processor; MOSIS; SCMOS technology; chip architecture; data compression; discrete cosine transform; high speed; highly pipelined; inverse DCT; Arithmetic; Circuit synthesis; Computer architecture; Data compression; Delay; Discrete cosine transforms; Discrete transforms; Distributed computing; Semiconductor device measurement; Throughput;
Conference_Titel :
Circuits and Systems, 1991., IEEE International Sympoisum on
Print_ISBN :
0-7803-0050-5
DOI :
10.1109/ISCAS.1991.176306
