• DocumentCode
    2826196
  • Title

    DCT architectures for HDTV

  • Author

    Jutand, F. ; Mou, Z.J. ; Demassieux, N.

  • Author_Institution
    Telecom Paris Univ., France
  • fYear
    1991
  • fDate
    11-14 Jun 1991
  • Firstpage
    196
  • Abstract
    The design of DCT (discrete cosine transform) circuits for HDTV (high-definition television) applications is addressed. Based on previous works on CCIR video image coding, several architectural solutions are presented and then compared. An optimization taking into account the potentials of present-day technologies and progress in arithmetic implementation and architecture makes it possible to implement a real-time DCT for HDTV implementation in roughly 40 mm2 (0.8-μm CMOS)
  • Keywords
    CMOS integrated circuits; computerised picture processing; digital signal processing chips; high definition television; real-time systems; telecommunications computing; 0.8 micron; CCIR video image coding; CMOS; DCT architectures; HDTV; arithmetic implementation; discrete cosine transform; high-definition television; real-time DCT; Arithmetic; Circuits; Computer architecture; Design optimization; Discrete cosine transforms; Encoding; HDTV; Image coding; Matrix decomposition; Read only memory;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Circuits and Systems, 1991., IEEE International Sympoisum on
  • Print_ISBN
    0-7803-0050-5
  • Type

    conf

  • DOI
    10.1109/ISCAS.1991.176307
  • Filename
    176307
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2826196