DocumentCode :
2826334
Title :
DSP architectures, algorithms, and code-generation: fission or fusion?
Author :
Simar, Ray, Jr.
Author_Institution :
Texas Instrum. Inc., Houston, TX, USA
fYear :
1997
fDate :
3-5 Nov 1997
Firstpage :
50
Lastpage :
59
Abstract :
Continuing dramatic improvements in semiconductor manufacturing processes are enabling radical new signal-processing architectures at the chip level. But how do we ensure that the radical becomes practical? The development of these new architectures must be coupled, a fusion, with clearly defined target applications, a thorough analysis of applicable signal processing algorithms, and significant advancements in code-generation technology. The TMS320C6x development program involved the codevelopment of the VelociTI architecture, a new code-generation environment, and a large set of representative benchmarks
Keywords :
digital signal processing chips; parallel architectures; DSP architectures; TMS320C6x development program; VelociTI architecture; algorithms; code-generation; code-generation environment; representative benchmarks; signal-processing architectures; Architecture; Assembly; Costs; Digital signal processing; High level languages; Pipeline processing; Protection; Signal processing algorithms; Silicon; VLIW;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Signal Processing Systems, 1997. SIPS 97 - Design and Implementation., 1997 IEEE Workshop on
Conference_Location :
Leicester
ISSN :
1520-6130
Print_ISBN :
0-7803-3806-5
Type :
conf
DOI :
10.1109/SIPS.1997.625686
Filename :
625686
Link To Document :
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