A knowledge-based compiler enhancing DSP internal parallelism

The authors describe code optimization techniques newly implemented for a DSP (digital signal processor) knowledge-based compiler which effectively enhances the DSP´s internal parallelism. A novel systematic parallel memory allocation method is introduced, and an efficient register allocation method is newly implemented in the rule-based code generator. An efficient loop code can be generated by using the developed code generator with a loop optimization method such as loop unrolling. With the above code optimization methods for DSPs, the compiler generates a code which is comparable to the code developed by programmers by hand for NEC77230/240 families