• DocumentCode
    2826459
  • Title

    A constructive procedure for processor clustering and arrays optimization

  • Author

    Bu, Jichun ; Deprettere, Ed F.

  • Author_Institution
    TNO-Inst. of Appl. Phys., Trondheim, Norway
  • fYear
    1991
  • fDate
    11-14 Jun 1991
  • Firstpage
    248
  • Abstract
    In previous work the authors have presented two processor-clustering techniques which have been shown to be key operations in the design of problem-size independent systolic/wavefront arrays. These clustering operations can be completely described in terms of so-called clustering vectors. In the present work, the authors present a generic, constructive, and yet simple procedure for the determination of the clustering vectors. Explicit expressions are derived for all the possible clustering vectors, which makes it possible to design fixed-size arrays in a parameterized way. It is shown how the clustering techniques can be used for the design of efficient arrays using a minimum number of processors
  • Keywords
    logic design; multiprocessor interconnection networks; parallel algorithms; systolic arrays; arrays optimization; clustering vectors; constructive procedure; fixed-size arrays; processor clustering; systolic arrays; wavefront arrays; Bandwidth; Clustering algorithms; Concurrent computing; Costs; Design methodology; Design optimization; Matrix decomposition; Physics; Pins; Systolic arrays;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Circuits and Systems, 1991., IEEE International Sympoisum on
  • Print_ISBN
    0-7803-0050-5
  • Type

    conf

  • DOI
    10.1109/ISCAS.1991.176320
  • Filename
    176320