Title :
Synthesis of zero input limit cycle free networks
Author :
Szczupak, Jacques ; Sheng, Chang Pi
Author_Institution :
Dept. of Electr. Eng., Catholic Univ. of Rio de Janeiro, Brazil
Abstract :
A method to synthesize digital filter structures free from zero-input limit-cycles is presented, based on the use of structurally bounded real realizations. A time-varying model is used for the network, allowing the analysis of zero-input granularity and overflow oscillations. Simple extensions to forced overflow situations are discussed. The method is illustrated for lower order networks
Keywords :
digital filters; limit cycles; digital filter design; forced overflow situations; limit cycle free networks; lower order networks; overflow limit-cycles; overflow oscillations; structurally bounded real realizations; time-varying model; zero-input granularity; zero-input limit-cycles; Digital filters; Equations; Fixed-point arithmetic; Lattices; Limit-cycles; Network synthesis; Passive networks; Quantization; Sufficient conditions; Transfer functions;
Conference_Titel :
Circuits and Systems, 1991., IEEE International Sympoisum on
Print_ISBN :
0-7803-0050-5
DOI :
10.1109/ISCAS.1991.176356
