DocumentCode
2827481
Title
Effect of inductance on interconnect propagation delay in VLSI circuits
Author
Ligocka, A. ; Bandurski, Wojciech
Author_Institution
Poznan Univ. of Technol., Poland
fYear
2004
fDate
9-12 May 2004
Firstpage
121
Lastpage
124
Abstract
In the paper the analytical formula for the propagation delay of CMOS gate driving a distributed RLC line was derived. It is shown that obtained formula is more accurate in some cases than used in literature. The main idea of the presented approach is based on the expansion of the voltage unit step response into Taylor series. The coefficients of this expansion are calculated in symbolical manner in frequency domain as the moments determined for infinite frequency.
Keywords
CMOS integrated circuits; VLSI; delays; inductance; integrated circuit interconnections; CMOS gate; Taylor series; VLSI circuits; distributed RLC line; frequency domain; inductance; infinite frequency; interconnect propagation delay; Capacitors; Circuit testing; Delay effects; Distributed parameter circuits; Inductance; Integrated circuit interconnections; Propagation delay; RLC circuits; Very large scale integration; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Signal Propagation on Interconnects, 2004. Proceedings. 8th IEEE Workshop on
Print_ISBN
0-7803-8470-9
Type
conf
DOI
10.1109/SPI.2004.1409024
Filename
1409024
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