Study on design method of boundary-scan circuit architecture based on Verilog language

Boundary-Scan is a standard architecture of DFT (Design For Testability), and is widely applied to board test, system debug and IC program. A general design method which adds the boundary-scan architecture into the logic core of circuit is proposed. Taken the IP core of 74290 as an example, the modular design of boundary-scan architecture is described by Verilog language, and verified in the corresponding boundary scan tests. The simulation and experiment results have proved the method is correctly and feasible.