Title :
Study on design method of boundary-scan circuit architecture based on Verilog language
Author :
Chen Shengjian ; Zhou Yin ; Xu Lei ; Luo Jian
Author_Institution :
Dept. of Control Eng., Acad. of Armored Force Eng., Beijing, China
Abstract :
Boundary-Scan is a standard architecture of DFT (Design For Testability), and is widely applied to board test, system debug and IC program. A general design method which adds the boundary-scan architecture into the logic core of circuit is proposed. Taken the IP core of 74290 as an example, the modular design of boundary-scan architecture is described by Verilog language, and verified in the corresponding boundary scan tests. The simulation and experiment results have proved the method is correctly and feasible.
Keywords :
boundary scan testing; design for testability; hardware description languages; industrial property; IP core; Verilog language; board test; boundary-scan circuit architecture; design for testability; logic core; system debug; Computer architecture; Hardware design languages; IP networks; Integrated circuits; Pins; Registers; Testing; Boundary-scan; DFT; IP core; Verilog;
Conference_Titel :
Mechanic Automation and Control Engineering (MACE), 2011 Second International Conference on
Conference_Location :
Hohhot
Print_ISBN :
978-1-4244-9436-1
DOI :
10.1109/MACE.2011.5988841
