FPGA Implementation of a Phase Locked Loop Based on Random Sampling

A phase locked loop (PLL) based on digital signal processing and random sampling is proposed in this paper. Field programmable gate array (FPGA) technology is used to implement a prototype. The random sampling scheme is used to reduce the sampling frequency requirements without aliasing effects. The possibility of sampling and processing at lower frequencies allows the implementation of complete-digital high-frequency systems, without limitations imposed by the analog to digital converter and the signal processing unit. The basic principles are presented, and the implemented algorithms are described. Experimental results show the PLL performance.