Built-in test pattern generation for high-performance circuits using twisted-ring counters

We present a new approach for built-in pattern generation based on the reseeding of twisted-ring counters (TRCs). The proposed technique embeds a precomputed deterministic test set for the circuit under test (CUT) in a short test sequence produced by a TRC. The TRC is designed using existing circuit flip-flops and does not add to hardware overhead beyond what is required for basic scan design. The test control logic is simple, uniform for all circuits, and can be shared among multiple CUTs. Furthermore, the proposed method requires no mapping logic between the TGC and the CUT; it imposes no additional performance penalty. Experimental results for the ISCAS benchmark circuits show that it is indeed possible to embed the entire precomputed test set in a TRC sequence using only a small number of seeds, especially if the test set contains many don´t-cares