DocumentCode
2827967
Title
Digital Signature Embedding Technique for IP Core Protection
Author
Castillo, Encarnacion ; Garcia, Alvaro ; Parrilla, Luis ; Morales, Diego P. ; Lloris, Antonio ; Meyer-Baese, UWe
Author_Institution
Granada Univ., Granada
fYear
2007
fDate
28-26 Feb. 2007
Firstpage
143
Lastpage
148
Abstract
The intellectual property protection of reusable design modules are becoming a problem with the expansion of this design strategy. This paper propose a new protection method for IP cores to be implemented over FPGAs. The aim is to protect the author rights of reusable IP cores by means of a digital signature that uniquely identifies both the original design and the design recipient. The technique relies on a procedure that spreads a digital signature in cells of look-up tables of designs at HDL design level, not increasing the area of the system. The technique includes a procedure for signature extraction that allows to detect the ownership right without interfering the normal operation of the system and requiring minimal modifications to the system. The IPP technique has been implemented on programmable devices, with negligible performance penalties.
Keywords
digital signatures; field programmable gate arrays; hardware description languages; industrial property; integrated circuit design; logic CAD; table lookup; FPGA; HDL design level; IP core protection; IPP technique; digital signature embedding technique; intellectual property protection; look-up tables; reusable design modules; Copyright protection; Design engineering; Design methodology; Digital signatures; Educational institutions; Embedded computing; Field programmable gate arrays; Hardware design languages; Intellectual property; Watermarking;
fLanguage
English
Publisher
ieee
Conference_Titel
Programmable Logic, 2007. SPL '07. 2007 3rd Southern Conference on
Conference_Location
Mar del Plata
Print_ISBN
1-4244-0606-4
Type
conf
DOI
10.1109/SPL.2007.371738
Filename
4234335
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